Various approaches are being adopted for developing integrated circuit arrangements with MOS transistors, which can be operated with operating voltages of less than 3 volts and which have reduced power consumption. One of these approaches proposes, instead of providing the conventionally used monocrystalline silicon wafer as a substrate, to provide an SOI substrate which comprises a monocrystalline silicon layer, an insulating layer arranged thereunder and a support wafer arranged under the latter.
MOS transistors are produced in the monocrystalline silicon layer of the SOI substrate. In this case, the active region of an MOS transistor is fully DC-insulated from adjacent components by etching away the surrounding silicon. This completely suppresses parasitic effects such as, for example, latch-up.
For the same operating speed, MOS circuits on an SOI substrate have a considerably lower power consumption than the corresponding circuit in a monocrystalline silicon wafer.
MESA etching of the monocrystalline silicon wafer has been proposed for lateral insulation of the active region of an MOS transistor in an SIO substrate (see, for example, Silicon-on-Insulator Technology, Jean Pierre Colinge, Kluwer Academic 1991, pages 94 to 98). In the vertical direction, the active region of the MOS transistor is insulated by the insulating layer arranged thereunder. In order to produce the MOS transistor, the surface of the MESA structure is provided with a gate oxide. A gate electrode, for example of polysilicon, is applied thereto. For contact with a gate line, the gate electrode extends partly over the side wall of the MESA. This requires gate side-wall control, which causes the undesirable, so-called "corner effect". This leads to non-ideal sub-threshold characteristics. Furthermore, oxide thinning occurs on the silicon edges of the MESA structure during the thermal oxidation for forming the gate dielectric. This can lead to premature oxide breakdown.
To avoid the side-wall effects, J. H. Choi et al., IEDM'94, page 645, has proposed the provision of a modified LOCOS insulation for lateral insulation of the active regions. In the LOCOS process, mechanical stresses are produced in the monocrystalline silicon layer. Furthermore, layer conformity is not guaranteed. Finally, it is difficult to scale the LOCOS process to structure sizes of less than 0.25 .mu.m. The achievable packing density is thus limited.
Although P. V. Gilbert et al., VLSI'95, page 37, has proposed a modified LOCOS process for thin-film SOI technology, with which structure sizes of less than 0.5 .mu.m can be achieved, the process is nevertheless expensive since it requires additional layer depositions and etching steps.
Furthermore, LOCOS processes lead to the formation of a so-called beak, which reduces the thickness of the monocrystalline silicon layer of the SOI substrate. At small layer thicknesses, as is recommendable for fast MOS transistors, this additionally leads to an increase in the impedance at the source/drain contact. J. M. Hwang et al., VLSI'94, page 33, has proposed to compensate such undesired yet unavoidable thinning of the silicon layer of the SOI substrate by selective growth of silicon.